1. Field of the Invention
Embodiments of the present invention relate to the field of power meters. Specifically, embodiments of the present invention relate to locking the sample rate of an analog to digital (ADC) converter to the line frequency of an input signal.
2. Related Art
Electrical power meters (EPMs) are widely used in residences and businesses to measure power consumption. Electrical power meters are known as watt-hour meters. Countries such as India, China, and other populous countries that are quickly industrializing require many EPMs to connect to the newly developed power grids. Other more industrialized countries are moving from mechanical measuring devices to electronic devices in order to measure power more effectively.
Due to the large number power meters being installed, this market has become very cost conscious, so much so that the power meters have become a commodity. In particular in developing countries, cost is a major factor in the decision to choose a power meter. As such, it is very desirable to make the power meter as inexpensive as possible.
Cost is primarily driven by competition since power meters are purchased by power companies and resold to consumers. Power companies evaluate competing designs and choose a cost effective solution based on a feature set and price point.
Power meters need to be accurate to avoid overfilling and undercharging. For example, most customers require a one percent or more of accuracy. Accuracy is driven by national standards that vary in detail from country to country, but are typically one-percent for residential meters. Errors more than one percent can greatly cut into a power distributor's profits.
A power meter measures the consumption of power. Power is the amount of energy consumed in a fixed period of time, as follows in equation 1:Power=energy/sec)  (1)Typically power is measured in watts which is defined as follows in equation 2:Watts=Joules(energy)/sec(time)  (2)
Therefore any power metering device must measure both energy and time to correctly calculate power consumption. Power use is accumulated continuously using a timing marker (e.g., second tick). Therefore, energy calculation and timing measurements must be precisely aligned for correct power accumulation.
In a power meter design, requirements for accuracy extend across a range of line frequencies. Power is measured by sampling voltage and current and from this calculating power use. Around the world, electrical power systems operate at nominal frequencies of 50 Hz and 60 Hz.
However, these frequencies drift and often are not exactly at their desired frequency. In the United States, this drift is small, but in other countries the frequency drift can be substantial. A power meter must track the power signal with its sampling system to maintain accuracy. If left unaccounted for, frequency mismatches between the input signal and the sample rate will cause errors that easily exceed allowable specifications.
Energy calculations are based on line cycle by line cycle accumulation and must be aligned with a related second tick. If this synchronization is ignored, an error exceeding the allowed accuracy of the meter may be easily introduced. Since line cycles are detected with either a peak or zero crossing of the input signal, an error of up to one percent could be present in the frequency calculation on a second by second basis.
Even if the power meter has a very accurate clock, if the sampling system does not track the power system, the power meter may exceed allowable specs. As a result, the power meter must track the power system frequency and adjust its sample clock periodically to minimize this error. Additionally, if the ADC is not synchronized to take a pre-defined integral number of cycles during a single AC power cycle (e.g., 60 cycles in a 60 Hz system), the misalignment may cause errors of up to one percent, which is out of specification tolerance. As a result, to achieve required accuracy in a power meter, it is important to manage the synchronization of ADC sample rate, line frequency detection and second tick.
In a conventional solution, the problem of frequency inaccuracy and errors in ADC sample periods are mitigated by increasing the sample frequency. This limits aliasing (errors due to under sampling) but requires a faster and more expensive ADC converter, which is undesirable in a cost sensitive power meter market.
In other conventional sampling systems, the ADC clock can be adjusted to provide the optimal sampling time. To provide the selectivity required, either a PLL (Phase Locked Loop) or a Direct Digital Synthesis system are used. Either of these systems requires additional (and more expensive) components, thus raising overall system cost, which again is undesirable in a cost sensitive power meter market.
In addition, in conventional solutions, the input line frequency can be measured by either peak detectors or zero crossing comparators to determine line cycle occurrence. Frequency calculation is conventionally determined by a count of line cycles per second. However, the time required to take n samples, where n, the over sample number, is not the same period of one complete input signal cycle, an error of up to one percent will be present in the frequency calculation on a second by second basis. In the case of a 60 Hz signal, the period would be 1/60 or 16.67 mSec.
It would be desirable to have an inexpensive and accurate solution to the problems of accuracy in power meters.